In the past, in a memory that adopts a double data rate (DDR) interface, reads out data from a memory cell array to a data amplifier via a main data line (MDQ), and transfers the data from the data amplifier to a data output circuit side via a data line (RWD), large bus width of the data lines is one of causes that prevent a reduction in a chip area.
The operation system in the past adopts a circuit configuration in which the number of bits read out from the memory cell array according to one read command and the bus width of the data lines are the same. Specifically, in the system in the past, data later in output order and data earlier in output order are read out in parallel from the memory cell array via the main data line and transferred to the data output circuit side via the data line in parallel. Therefore, the bus width of the main data line and the bus width of the data line are the same.
In such a circuit configuration, the bus width of the data line increases as the number of prefetches increases. Therefore, the problem of the cause of prevention of a reduction in a chip area is more conspicuous as the generation of DDR advances to DDR2 and DDR3.
Japanese Patent Application Laid-Open No. 2003-308694 discloses a semiconductor device that divides data transferred by an internal data bus having large bus width and outputs the divided data to an external data bus. Japanese Patent Application Laid-Open No. 2000-10857 discloses a memory control device including a data selector that divides an output data bus of a memory and selects and outputs divided data and enabling partial use of the output data bus.
However, the invention disclosed in Japanese Patent Application Laid-Open No. 2003-308694 can reduce the bus width of the external data bus of the semiconductor device compared with the bus width of the internal data bus but cannot reduce the bus with of the internal data bus. The invention disclosed in Japanese Patent Application Laid-Open No. 2000-10857 simply enables partial use of the output data bus of the memory and does not reduce the bus width of the internal bus of the memory. In other words, Japanese Patent Application Laid-Open No. 2003-308694 and Japanese Patent Application Laid-Open No. 2000-10857 disclose nothing concerning a reduction in the bus width of the data line as a part of the internal bus of the semiconductor device. Therefore, the problem of an increase in the bus width of the data line involved in an increase in the number of prefetches cannot be solved.